272 lines
7.8 KiB
C
Executable File
272 lines
7.8 KiB
C
Executable File
/*
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Copyright (c), 2001-2022, Shenshu Tech. Co., Ltd.
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*/
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#ifndef OT_MIPI_RX_H
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#define OT_MIPI_RX_H
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#include "osal_ioctl.h"
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#ifdef __cplusplus
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extern "C"{
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#endif /* __cplusplus */
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typedef unsigned int combo_dev_t;
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typedef unsigned int sns_rst_source_t;
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typedef unsigned int sns_clk_source_t;
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#define MIPI_LANE_NUM 8
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#define LVDS_LANE_NUM 8
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#define WDR_VC_NUM 4
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#define SYNC_CODE_NUM 4
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#define MIPI_RX_MAX_DEV_NUM 4
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#define SNS_MAX_CLK_SOURCE_NUM 4
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#define SNS_MAX_RST_SOURCE_NUM 4
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#define MAX_EXT_DATA_TYPE_NUM 3
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#ifdef OT_MIPI_DEBUG
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#define ot_msg(x...) \
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do { \
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osal_printk("%s->%d: ", __FUNCTION__, __LINE__); \
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osal_printk(x); \
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osal_printk("\n"); \
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} while (0)
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#else
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#define ot_msg(args...) \
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do { \
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} while (0)
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#endif
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#define ot_err(x...) \
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do { \
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osal_printk("%s(%d): ", __FUNCTION__, __LINE__); \
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osal_printk(x); \
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} while (0)
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#define mipi_rx_unused(x) ((void)x)
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typedef enum {
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LANE_DIVIDE_MODE_0 = 0, /* 8lane */
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LANE_DIVIDE_MODE_1 = 1, /* 4lane + 4lane */
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LANE_DIVIDE_MODE_2 = 2, /* 4lane + 2lane +2lane */
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LANE_DIVIDE_MODE_3 = 3, /* 2lane + 2lane + 2lane + 2lane */
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LANE_DIVIDE_MODE_BUTT
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} lane_divide_mode_t;
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typedef enum {
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WORK_MODE_LVDS = 0x0,
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WORK_MODE_MIPI = 0x1,
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WORK_MODE_CMOS = 0x2,
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WORK_MODE_BT1120 = 0x3,
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WORK_MODE_SLVS = 0x4,
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WORK_MODE_BUTT
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} work_mode_t;
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typedef enum {
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INPUT_MODE_MIPI = 0x0, /* mipi */
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INPUT_MODE_SUBLVDS = 0x1, /* SUB_LVDS */
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INPUT_MODE_LVDS = 0x2, /* LVDS */
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INPUT_MODE_HISPI = 0x3, /* HISPI */
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INPUT_MODE_BUTT
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} input_mode_t;
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typedef enum {
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MIPI_DATA_RATE_X1 = 0, /* output 1 pixel per clock */
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MIPI_DATA_RATE_X2 = 1, /* output 2 pixel per clock */
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MIPI_DATA_RATE_BUTT
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} mipi_data_rate_t;
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typedef struct {
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int x;
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int y;
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unsigned int width;
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unsigned int height;
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} img_rect_t;
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typedef struct {
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unsigned int width;
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unsigned int height;
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} img_size_t;
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typedef enum {
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DATA_TYPE_RAW_8BIT = 0,
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DATA_TYPE_RAW_10BIT,
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DATA_TYPE_RAW_12BIT,
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DATA_TYPE_RAW_14BIT,
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DATA_TYPE_RAW_16BIT,
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DATA_TYPE_YUV420_8BIT_NORMAL,
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DATA_TYPE_YUV420_8BIT_LEGACY,
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DATA_TYPE_YUV422_8BIT,
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DATA_TYPE_YUV422_PACKED, /* yuv422 8bit transform user define 16bit raw */
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DATA_TYPE_BUTT
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} data_type_t;
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typedef struct {
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combo_dev_t devno;
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unsigned int num;
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unsigned int ext_data_bit_width[MAX_EXT_DATA_TYPE_NUM];
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unsigned int ext_data_type[MAX_EXT_DATA_TYPE_NUM];
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} ext_data_type_t;
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/* MIPI D_PHY WDR MODE defines */
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typedef enum {
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OT_MIPI_WDR_MODE_NONE = 0x0,
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OT_MIPI_WDR_MODE_VC = 0x1, /* Virtual Channel */
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OT_MIPI_WDR_MODE_DT = 0x2, /* Data Type */
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OT_MIPI_WDR_MODE_DOL = 0x3, /* DOL Mode */
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OT_MIPI_WDR_MODE_BUTT
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} mipi_wdr_mode_t;
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typedef struct {
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data_type_t input_data_type; /* data type: 8/10/12/14/16 bit */
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mipi_wdr_mode_t wdr_mode; /* MIPI WDR mode */
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short lane_id[MIPI_LANE_NUM]; /* lane_id: -1 - disable */
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union {
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short data_type[WDR_VC_NUM]; /* attribute of MIPI WDR mode. AUTO:mipi_wdr_mode_t:OT_MIPI_WDR_MODE_DT; */
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};
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} mipi_dev_attr_t;
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typedef enum {
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OT_LVDS_WDR_MODE_NONE = 0x0,
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OT_LVDS_WDR_MODE_2F = 0x1,
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OT_LVDS_WDR_MODE_3F = 0x2,
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OT_LVDS_WDR_MODE_4F = 0x3,
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OT_LVDS_WDR_MODE_DOL_2F = 0x4,
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OT_LVDS_WDR_MODE_DOL_3F = 0x5,
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OT_LVDS_WDR_MODE_DOL_4F = 0x6,
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OT_LVDS_WDR_MODE_BUTT
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} lvds_wdr_mode_t;
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typedef enum {
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LVDS_SYNC_MODE_SOF = 0, /* sensor SOL, EOL, SOF, EOF */
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LVDS_SYNC_MODE_SAV, /* SAV, EAV */
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LVDS_SYNC_MODE_BUTT
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} lvds_sync_mode_t;
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typedef enum {
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LVDS_VSYNC_NORMAL = 0x00,
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LVDS_VSYNC_SHARE = 0x01,
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LVDS_VSYNC_HCONNECT = 0x02,
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LVDS_VSYNC_BUTT
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} lvds_vsync_type_t;
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typedef struct {
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lvds_vsync_type_t sync_type;
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/* hconnect vsync blanking len, valid when the sync_type is LVDS_VSYNC_HCONNECT */
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unsigned short hblank1;
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unsigned short hblank2;
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} lvds_vsync_attr_t;
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typedef enum {
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LVDS_FID_NONE = 0x00,
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LVDS_FID_IN_SAV = 0x01, /* frame identification id in SAV 4th */
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LVDS_FID_IN_DATA = 0x02, /* frame identification id in first data */
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LVDS_FID_BUTT
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} lvds_fid_type_t;
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typedef struct {
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lvds_fid_type_t fid_type;
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/* Sony DOL has the Frame Information Line, in DOL H-Connection mode,
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should configure this flag as false to disable output the Frame Information Line */
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unsigned char output_fil;
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} lvds_fid_attr_t;
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typedef enum {
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LVDS_ENDIAN_LITTLE = 0x0,
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LVDS_ENDIAN_BIG = 0x1,
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LVDS_ENDIAN_BUTT
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} lvds_bit_endian_t;
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typedef struct {
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data_type_t input_data_type; /* data type: 8/10/12/14 bit */
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lvds_wdr_mode_t wdr_mode; /* WDR mode */
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lvds_sync_mode_t sync_mode; /* sync mode: SOF, SAV */
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lvds_vsync_attr_t vsync_attr; /* normal, share, hconnect */
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lvds_fid_attr_t fid_attr; /* frame identification code */
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lvds_bit_endian_t data_endian; /* data endian: little/big */
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lvds_bit_endian_t sync_code_endian; /* sync code endian: little/big */
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short lane_id[LVDS_LANE_NUM]; /* lane_id: -1 - disable */
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/* each vc has 4 params, sync_code[i]:
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sync_mode is SYNC_MODE_SOF: SOF, EOF, SOL, EOL
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sync_mode is SYNC_MODE_SAV: invalid sav, invalid eav, valid sav, valid eav */
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unsigned short sync_code[LVDS_LANE_NUM][WDR_VC_NUM][SYNC_CODE_NUM];
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} lvds_dev_attr_t;
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typedef struct {
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combo_dev_t devno; /* device number */
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input_mode_t input_mode; /* input mode: MIPI/LVDS/SUBLVDS/HISPI/DC */
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mipi_data_rate_t data_rate;
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img_rect_t img_rect; /* MIPI Rx device crop area (corresponding to the original sensor input image size) */
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union {
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mipi_dev_attr_t mipi_attr; /* attribute of MIPI interface. AUTO:input_mode_t:INPUT_MODE_MIPI; */
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lvds_dev_attr_t lvds_attr; /* attribute of MIPI interface. AUTO:input_mode_t:INPUT_MODE_LVDS; */
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};
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} combo_dev_attr_t;
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typedef enum {
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PHY_CMV_GE1200MV = 0x00,
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PHY_CMV_LT1200MV = 0x01,
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PHY_CMV_BUTT
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} phy_cmv_mode_t;
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typedef struct {
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combo_dev_t devno;
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phy_cmv_mode_t cmv_mode;
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} phy_cmv_t;
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#define OT_MIPI_IOC_MAGIC 'm'
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/* init data lane, input mode, data type */
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#define OT_MIPI_SET_DEV_ATTR _IOW(OT_MIPI_IOC_MAGIC, 0x01, combo_dev_attr_t)
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/* set phy common mode voltage mode */
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#define OT_MIPI_SET_PHY_CMVMODE _IOW(OT_MIPI_IOC_MAGIC, 0x04, phy_cmv_t)
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/* reset sensor */
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#define OT_MIPI_RESET_SENSOR _IOW(OT_MIPI_IOC_MAGIC, 0x05, sns_rst_source_t)
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/* unreset sensor */
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#define OT_MIPI_UNRESET_SENSOR _IOW(OT_MIPI_IOC_MAGIC, 0x06, sns_rst_source_t)
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/* reset mipi */
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#define OT_MIPI_RESET_MIPI _IOW(OT_MIPI_IOC_MAGIC, 0x07, combo_dev_t)
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/* unreset mipi */
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#define OT_MIPI_UNRESET_MIPI _IOW(OT_MIPI_IOC_MAGIC, 0x08, combo_dev_t)
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/* set mipi hs_mode */
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#define OT_MIPI_SET_HS_MODE _IOW(OT_MIPI_IOC_MAGIC, 0x0b, lane_divide_mode_t)
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/* enable mipi clock */
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#define OT_MIPI_ENABLE_MIPI_CLOCK _IOW(OT_MIPI_IOC_MAGIC, 0x0c, combo_dev_t)
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/* disable mipi clock */
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#define OT_MIPI_DISABLE_MIPI_CLOCK _IOW(OT_MIPI_IOC_MAGIC, 0x0d, combo_dev_t)
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/* enable sensor clock */
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#define OT_MIPI_ENABLE_SENSOR_CLOCK _IOW(OT_MIPI_IOC_MAGIC, 0x10, sns_clk_source_t)
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/* disable sensor clock */
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#define OT_MIPI_DISABLE_SENSOR_CLOCK _IOW(OT_MIPI_IOC_MAGIC, 0x11, sns_clk_source_t)
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#define OT_MIPI_SET_EXT_DATA_TYPE _IOW(OT_MIPI_IOC_MAGIC, 0x12, ext_data_type_t)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* OT_MIPI_RX_H */
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